1. Field of the Invention
The present invention relates to a differential amplifier used in a phase locked loop (PLL) and a delay locked loop (DLL).
2. Description of the Related Art
In a phase locked loop (PLL), a complementary metal oxide silicon (CMOS) differential amplifier is used to convert a small signal outputted from a voltage controlled oscillator (VCO) to a signal having a level used in a CMOS circuit. The CMOS differential amplifier receives a differential input signal having a phase difference of 180 degrees.
Two phase signals are selected among a plurality of phase signals outputted from the voltage-controlled oscillator (VCO) and amplified by the CMOS differential amplifier. The amplified output signal of the CMOS differential amplifier is provided to a duty cycle correction (DCC) circuit to correct the duty cycle thereof. The DCC circuit is employed in the PLL or a delayed locked loop (DLL) to adjust a duty cycle of the output signal of the PLL or DLL to 50%
To prevent duty cycle distortion in an output signal of the DCC circuit, which corresponds to the output signal of the CMOS differential amplifier, the output signal of the CMOS differential amplifier that is inputted to the DCC circuit is preferred to have a duty cycle of approximately 50%. Therefore, the signals inputted to the CMOS differential amplifier is preferred to be a differential signal having a phase difference of 180 degrees from each other.
When even-numbered phase signals are outputted from the VCO and the even-numbered phase signals respectively have, for example, a phase of 0 degrees, a phase of 90 degrees, a phase of 180 degrees and a phase of 270 degrees, among the even-numbered phase signals, two phase signals having a phase difference of 180 degrees (e.g., a phase signal having a phase of 90 degrees and a phase signal having a phase of 270 degrees) can be provided as differential input signals of the CMOS differential amplifier.
FIG. 1 is a block diagram illustrating a conventional voltage-controlled oscillator (VCO) that outputs odd-numbered phase signals.
Referring to FIG. 1, odd-numbered phase signals, for example, five phase signals including a phase signal “a” having a phase of 0 degrees, a phase signal “b” having a phase of 72 degrees, a phase signal “c” having a phase of 144 degrees, a phase signal “d” having a phase of 216 degrees and a phase signal “e” having a phase of 288 degrees are outputted from respective CMOS inverter amplifiers 10 of the VCO.
In the VCO, the phase difference between two phase signals that are inputted to the respective CMOS differential amplifiers 20 is not 180 degrees. Accordingly, although the output signal of the CMOS differential amplifier 20 is provided to the DCC circuit 30 to correct the duty cycle thereof, the duty cycle of an output signal of the DCC circuit 30, which corresponds to the output signal of the CMOS differential amplifier 20, can be distorted.
In addition, when using a phase interpolation circuit to provide differential signals having a phase difference of 180 degrees using odd-numbered phase signals outputted from the VCO, power consumption can be increased and a load of the VCO can be increased by the interpolation circuit.